1. Field of the Invention
This invention relates to the field of superscalar microprocessors and, more particularly, to the dispatch and scheduling of instructions to execution units within a microprocessor.
2. Description of the Related Art
Superscalar microprocessors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design. As used herein, the term “clock cycle” refers to an interval of time accorded to various stages of an instruction processing pipeline within the microprocessor. Storage devices (e.g. registers and arrays) capture their values according to the clock cycle. For example, a storage device may capture a value according to a rising or falling edge of a clock signal defining the clock cycle. The storage device then stores the value until the subsequent rising or falling edge of the clock signal, respectively. The term “instruction processing pipeline” is used herein to refer to the logic circuits employed to process instructions in a pipelined fashion. Although the pipeline may be divided into any number of stages at which portions of instruction processing are performed, instruction processing generally comprises fetching the instruction, decoding the instruction, executing the instruction, and storing the execution results in the destination identified by the instruction.
In order to increase performance, superscalar microprocessors often employ a multiple dispatch model of instruction processing. The multiple dispatch model refers to the ability to dispatch multiple instructions for execution simultaneously. This is in contrast to the single dispatch model, wherein a single instruction is dispatched for execution at one time. When multiple instructions are dispatched simultaneously, it is possible for one or more of the simultaneously dispatched instructions to require a specialized execution unit. This may arise when a given instruction requires an execution unit that performs a particular function that the other execution units may not perform. For example, integer multiply instructions may only be performed by the execution unit in position two or a floating-point compare may only be performed by the execution unit in position three. Currently, there may be no way for the scheduling and dispatch logic to know with which execution position a particular instruction is associated. One common way to force an instruction to a given execution position is to designate this type of instruction as a microcode instruction.
When a microcode instruction is dispatched to a particular execution position, no other instructions may be dispatched for execution by the remaining execution units during that dispatch cycle. Thus, depending on how many special instructions exist and when instructions are issued to the execution units, execution slots in various stages of the execution pipelines may go unused. This may lead to inefficiencies due to the various pipeline stages not being full.